Work in progress

Here is a list of some of the projects that are currently active. There are many more not listed here.

Verilog-A,AMS, VHDL-AMS

The input language is being modified to accept both of these industry standard languages. The algorithms already support what is needed for the full -AMS. Eventually, Gnucap will support both of these as native, both compiled and interpreted. Since this is in great demand, and will solve the problem of a lack of models, it is the highest priority.

Model Compiler

The gnucap model compiler already makes model addition much easier than other simulators. In general, it does a good job, but there are a few pieces missing. The most significant missing piece is automatic differentiation of the evaluation functions. The gather/scatter portion also needs improvement. The original work was done in a new language, to get the job done quickly. The next refinement is to take Verilog-A as an input language.

Multi-rate

The highest research priority is the completion of multi-rate transient analysis. This should improve the performance in transient analysis by using different time steps in different parts of the circuit. This research is being done at Kettering University, in Flint, Michigan, USA.

IBIS

I have the code for IBIS support mostly complete except for waveform generation. Some help in completing this part would make available the first free simulator with IBIS support. This has been a high priority, but has moved down due to funding issues, simply that the models and model compiler are more important. As of now, it exists as a stand-alone translator.