As an example of how to customize indentation, let’s change the style of the example above from:
1: inverter : process 2: begin 3: q <= not d; 4: wait on d; 5: end inverter;
to:
1: inverter : process 2: begin 3: q <= not d; 4: wait on d; 5: end inverter;
In other words, we want to change the indentation of the statements inside the inverter process. Notice that the construct we want to change starts on line 3. To change the indentation of a line, we need to see which syntactic component affect the offset calculations for that line. Hitting C-c C-x on line 3 yields:
((statement-block-intro . 20))
So we know that to change the offset of the first signal assignment, we need to
change the indentation for the statement-block-intro
syntactic
symbol. To do this interactively, just hit C-c O
(vhdl-set-offset
). This prompts you for the syntactic symbol to
change, providing a reasonable default. In this case, the default is
statement-block-intro
, which is just the syntactic symbol we want to
change!
After you hit return, VHDL Mode will then prompt you for the new
offset value, with the old value as the default. The default in this
case is ‘+’, so hit backspace to delete the ‘+’, then hit
‘++’ and RET. This will associate an offset of twice the
basic indent with the syntactic symbol statement-block-intro
in
the vhdl-offsets-alist
variable.
To check your changes quickly, just enter M-x vhdl-indent-defun to reindent the entire function. The example should now look like:
1: inverter : process 2: begin 3: q <= not d; 4: wait on d; 5: end inverter;
Notice how just changing the offset on line 3 is all we needed to do. Since the other affected lines are indented relative to line 3, they are automatically indented the way you’d expect. For more complicated examples, this may not always work. The general approach to take is to always start adjusting offsets for lines higher up in the file, then re-indent and see if any following lines need further adjustments.